Macronix Plans Low-Cost <span style='color:red'>3D NAND</span>
Miin Wu believes that he can cut 3D NAND prices by a third. The founder of Macronix is raising funds for a three-year effort that is both ambitious and pragmatic.The NOR and ROM maker seeks funds to expand by a little more than 10% of its current capacity of about 400,000 12-inch equivalent wafers/month. An extra 50,000 wafers/month will initially be in traditional 3D NAND. Once it establishes a customer base, it will ramp a novel architecture that it claims sports 30% lower cost per bit.If all goes well, the company aims to release its first chips in in a little more than two years. Miin Wu was in Silicon Valley recently to discuss with equipment makers details of key etch tools needed to make competitive 3D NAND parts.“Right now, all my R&D money is spent on 3D NAND,” said Miin Wu, noting that he expects to make his own controllers, too. “If I can build a 50,000-wafer capacity, I can compete and make money, but for our full ROI, we need multiples of that, so we will need to expand.”Macronix is not the only wannabe in the burgeoning market for 3D NAND. China’s Yangtze Memory Technology Co. aims to deliver 256-Gbit chips late next year supporting data rates up to 3.0 Gbits/s using a proprietary Xstacking technology. YMTC was founded in 2016 with a whopping $24 billion in funding, leveraging the 12-inch fabs of China’s XMC in Wuhan.YMTC plans to be in volume production of conventional 32-layer NAND chips by October. If all goes well, in a little more than a year, it could be producing chips at a rate of 100,000 wafers/month in the first phase of a new fab with a second phase planned to triple capacity, fueling plans to take 10% to 20% of the worldwide NAND market.It’s a big, risky bet to gain a position in a highly competitive field. Just last month, SK Hynix announced that it will sample before the end of the year a 512-Gbit version of its 96-layer chips and a Tbit version before June. Larger rivals Samsung and Toshiba are already shipping similar parts today. The top vendors, which include Micron, are said to be well on their way to cracking the 100-layer level with plans extending to hundreds of levels.Despite the heady competition, Macronix “has a good opportunity to focus on lower-density parts that major vendors obsolete — in a shortage, that’s a great place to be,” said analyst Jim Handy of Objective Analysis, who estimates that the flash market will hit $58 billion this year, up 23% over 2017.That’s the kind of position in trailing-edge memories that Macronix has traditionally pursued. This time around, however, Miin Wu said that he aims to deliver 3D NAND parts at the same density but lower costs as rivals.Handy said that the goal would challenge the Taiwan company’s business model that, to date, has focused more on high-mix, low-volume products. Success will also depend on the state of NAND ASPs, which have been declining from 27 cents/GByte to 20 cents/GB, noted Handy.“I believe that memory can be the other strength of Taiwan,” said Miin Wu, who founded Macronix in 1989, when TSMC was just two years old.Today, TSMC is producing state-of-the-art SoCs at 7 nm, while Macronix is best-known as a leader in older memory products such as NOR flash and ROMs made in 90- and 35-nm nodes. That said, Macronix has its share of innovations with more than 7,600 patents, said Miin Wu, who helped design the EEPROM while at Intel in the 1970s.Macronix plans a number of stops along the way to its 3D NAND dreams. It plans to sample 4-GByte eMMC NAND by the end of the year. It’s also driving NOR down to 1.2 V for low-power IoT chips with standby power measured in nanoamps.Nintendo remains its largest customer overall. In China, Huawei is its largest customer and likely one of the first to use its eMMC chips in products such as base stations.Macronix described its Single-Gate Vertical Channel architecture for 3D NAND at IEDM. Click to enlarge. (Source: Macronix)
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Release time:2018-09-19 00:00 reading:1086 Continue reading>>
YMTC to Detail <span style='color:red'>3D NAND</span> Chips
Yangtze Memory Technologies Co., Ltd. (YMTC) will unveil next week its latest 3D NAND chips. The talk by chief executive Simon Yang at the Flash Memory Summit here will mark the first public discussion of an effort from China to produce leading-edge memory chips.YTMC will describe what it calls Xtacking as an approach to 3D NAND that delivers a “speed-up to DRAM DDR4 while delivering industry-leading bit density, marking a quantum leap for the NAND market.” Xtacking “enables parallel processing of the NAND array and periphery … a modular approach [that will] shorten the time-to-market for new generations of 3D NAND and open the possibility for customized NAND flash products,” according to a press statement.The company, described as the pride of China, has long been seen as one of the country’s most likely candidates to deliver a commercially viable mainstream memory chip. It was founded in 2016 with a whopping $24 billion in funding, leveraging the 12-inch fabs of China’s XMC in Wuhan.YMTC announced a 32-layer 3D NAND chip last year and said that it would ship this year a 48-layer version. In February, a Wall Street analyst said that YMTC’s yields on its 32-layer NAND chips were still very low, suggesting that a 48-layer part could still be many months from general availability.If YMTC’s target remains the same, it will be one or two steps behind larger rivals. Intel, Micron, Samsung, and Toshiba/WD have announced or are shipping 96-layer, 4-bit-per-cell devices. Samsung said that its chips have DDR4-like speeds at 1.4 Gbits/second.The YMTC news comes at a time of heightened trade tensions between the U.S. and China, where semiconductors have been a particular flash point.Industry trade groups have long lobbied the U.S. government to help set a level playing field in China. The China government is investing heavily in chips and requiring foreign firms to transfer their technology in exchange for market access, they claim. However, they protested the Trump administration’s recent tariffs as an ineffective and even harmful approach.YMTC said that its Xtacking chips will be used in UFS as well as client and enterprise solid-state drives for use in smartphones, PCs, and data centers. The company claims that it has “help from customers, industry partners, and standard bodies [to enable] a whole new chapter in high-performance NAND solutions.”Ironically, Samsung, which was the first company to announce commercial 3D NAND chips at the Flash Memory Summit, is not participating in the event this year. The gap leaves YMTC an opening to be the talk of the show at which all the other major flash vendors are participating.
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Release time:2018-08-03 00:00 reading:2553 Continue reading>>
Toshiba Memory to Build New Fab to Produce BiCS <span style='color:red'>3D NAND</span>
Toshiba Memory Corp., which is set to become independent from Toshiba in a few days, has announced their intention to start construction of a new BiCS 3D NAND fab in July. TMC expects Western Digital to participate in the new project. Overall, this is the latest in a number of NAND fab announcements across the industry in the last year that, at long last, signals surging interest in building additional capacity.The new fab will be located near Kitakami City, Iwate prefecture. By contrast, the existing NAND flash production facilities operated by TMC and Western Digital are located near Yokkaichi, Mie prefecture. Traditionally for Japan, the new fab will feature a quake absorbing structure and an environmentally friendly design, which includes materials used and energy efficient production equipment. Just like the Fab 6, the new production facility will use an AI-powered production system to boost productivity.Toshiba expects to complete the building sometimes in 2019 (most probably in summer 2019 as it takes around a year to construct a fab building) and then start with equipment move-in. This process usually takes two to three quarters, so expect the new fab to come online in 2020, if everything goes as planned.Until the company makes its final decision regarding the manufacturing tools to be used, the actual production capacity of the new fab is unknown. Meanwhile, decisions regarding equipment will be made based on multiple factors, including predicted demand for NAND and Western Digital’s participation in the project. Speaking of Western Digital. Late last year Western Digital announced that it would participate in building the fab in Iwate, but so far, the company has not made any announcements regarding its exact plans on the matter.Toshiba last week announced that it had received all the required anti-trust regulatory approvals regarding its sale of Toshiba Memory Corp. (TMC) to Pangea consortium of investors. The last regulator to approve the $18-billion transaction was China. The deal is now expected to close on June 1, as planned by the Japanese company.
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Release time:2018-05-30 00:00 reading:3111 Continue reading>>
Micron and Intel extend leadership in <span style='color:red'>3D NAND</span> flash memory
Micron Technology and Intel have announced production and shipment of the industry’s first 4bits/cell 3D NAND technology. Leveraging a proven 64-layer structure, the new 4bits/cell NAND technology achieves 1 terabit (Tb) density per die, the world's highest-density flash memory.The companies have also announced development progress on the third-generation 96-tier 3D NAND structure, providing a 50 percent increase in layers. These advancements in the cell structure continue the companies’ leadership in producing the world’s highest Gb/mm2 areal density.Both NAND technology advancements use CMOS under the array (CuA) technology to reduce die sizes and deliver improved performance when compared to competitive approaches.By leveraging four planes vs the competitors’ two planes, the new Intel and Micron NAND flash memory can write and read more cells in parallel, which delivers faster throughput and higher bandwidth at the system level.The new 64-layer 4bits/cell NAND technology enables denser storage in a smaller space, bringing significant cost savings for read-intensive cloud workloads and is well-suited for consumer and client computing applications, providing cost-optimised storage solutions."With the introduction of 64-layer 4bits/cell NAND technology, we are achieving 33 percent higher array density compared to TLC, which enables us to produce the first commercially available 1 terabit die in the history of semiconductors," said Micron Executive Vice President, Technology Development, Scott DeBoer. "We’re continuing flash technology innovation with our 96-layer structure, condensing even more data into smaller spaces, unlocking the possibilities of workload capability and application construction."“Commercialisation of 1Tb 4bits/cell is a big milestone in NVM history and is made possible by numerous innovations in technology and design that further extend the capability of our Floating Gate 3D NAND technology,” said RV Giridhar, Intel vice president, Non-Volatile Memory Technology Development. “The move to 4bits/cell enables compelling new operating points for density and cost in data centre and client storage.”
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Release time:2018-05-23 00:00 reading:1280 Continue reading>>
Micron Talks <span style='color:red'>3D NAND</span> Sans Intel
  On the heels of shaking up its partnership with Intel, Micron Technology Chief Technology OfficerErnie Maddock took the stage at the J.P. Morgan 16th Annual Tech Forum at the 2018 International CES to field questions about the road ahead.  In a Q&A and session moderated by Harlan Sur, analyst for U.S. Semiconductor and Semiconductor Capital Equipment Research at J.P. Morgan, Maddock emphasized that the update to Micron's working relationship with Intel is only related to NAND development.  At the top of the week, the companies announced they have mutually agreed to work independently on future generations of 3D NAND. Micron and Intel will complete development of their third-gen 3D NAND technology toward the end of the year and into 2019. Maddock said based on evolving roadmaps and the needs of each company's respective markets, it made sense to diverge for the next node.  The end of the 3D NAND joint development agreement with Intel was “thoughtfully and carefully considered," and doesn't affect shared manufacturing facilities, he said. The companies are still collaborating on 3D Xpoint, a technology that got little attention in the Q and A despite a comment from Micron CEO Sanjay Mehrotra during the company's recent quarterly webcast that it would have more news.  In November, Intel and Micron announced the completed expansion of its IM Flash facilities in Lehi, Utah, that will produce 3D XPoint, which is being used in Intel Optane technology, including Optane memory for clients, the Optane SSD 900P series and new capacities and form factors of the Optane SSD DC P4800X series.  Sur noted 3D NAND has been a bright spot for Micron. Having struggled with planar NAND, once 3D NAND got started, the company's overall execution improved on several fronts. He said Micron's split from Intel on that technology might be a good decision given the company's current success. It does, however, raise questions about the impact on R&D momentum going forward.  Maddock said Micron has “arm's length agreements" to sell products to partners that will roll off in 2018 and into 2019. In the grand scheme, it will be bearing more R&D expenses, so it will have to rationalize in this new world, including figuring out how to do things better. He said Micron is now ramping up second-gen 3D NAND and has great products on third-gen technology slated for 2020-21, including the expansion of its SSD portfolio and managed NAND, particularly for the notebook and embedded markets.  Sur noted the timing of the fork from Intel also comes at time when Micron is getting more traction in the enterprise and cloud segments, where it's traditionally had a small share in the SSD market. In its last quarter, Micron benefitted from favorable pricing environments for both DRAM and NAND, hitting record revenues for its SSDs and increasing its share of the market. Maddock foresees a future where Micron's share moves into the double digits as it executes its roadmap and broadens its portfolio.  But as Sur noted, this growth comes at a time when there's a potential oversupply of 3D NAND around the corner after a shortage that created a beneficial pricing environment for Micron. “Our belief is there is ample demand for the level of bit supply," Maddock said, and that there's “ample room" for price reduction without being detrimental to margins.  DRAM pricing is also continuing to hold, said Sur and strong in all segments for Micron. Maddock said both the enterprise and hyperscale server markets have generated strong demand for DRAM, and mobile is on track for another good year. With cloud and data center CAPEX seeing 30 percent growth, Sur asked if it could outpace mobile. Maddock said the gap is quite narrow and too close to call.  Micron is also bullish on autonomous vehicles and edge computing, such as security devices and smart home appliances. Micron doesn't see these streams of demand as being separate. More content on mobile phones means more demand on servers, said Maddock. Even vehicles that aren't completely autonomous are generating more data from safety systems and digital dashboards, and that data is going to the cloud. He said the company has positioned itself well in the automotive market, where qualification times are long and rigorous, so Micron's goal is to help customer shorten those times wherever possible to get the latest and greatest technology sooner.  Home automation and edge devices are already carrying a reasonable amount of content, said Sur, noting that Micron is in the popular Amazon Echo, and it's a significant market opportunity. An important trend, said Maddock, is that a device often starts simple, but as it gets more popular, customers want more sophistication, and that means more memory.  Maddock himself joined Micron two-and-half years ago when the company was just starting 20nm DRAM. Now it's ramping 1x, and although competitors remain ahead, the gap has closed. “We have travelled a fairly good distance," Maddock said.  In addition, Micron's ability to put CMOS under the array enables it to fight above its weight in 3D NAND and expects the architecture to be viable for several generations. "The transition to 3D NAND was a defining moment for the company," he added.
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Release time:2018-01-12 00:00 reading:1282 Continue reading>>
64 Layers is <span style='color:red'>3D NAND</span>'s Sweet Spot
  Siva Sivaram can only speak for Western Digital, but he sees 64-layer 3D NAND as crossing the threshold to being more cost effective than planar NAND.  In a recent telephone interview with EE Times, the company's executive vice president of memory technology described 64-Layer 3D NAND as a "seminal technology” that will find its way into more than 50 of Western Digital's product lines. He anticipates half of Western Digital's bit output will be 3D NAND this calendar year, more than 75 percent of which will be 64-layer 3D NAND. "Sixty-four-layer is the first point where we truly think it's cost competitive with 2D NAND.”  The company recently announced what it called the world's first client SSDs built with its 64-layer 3D NAND technology. The WD Blue 3D NAND SATA SSD is aimed at DIY enthusiasts, resellers and system builders, while the SanDisk Ultra 3D SSD is targeted at gaming and creative enthusiasts who want to improve their PCs. Both will be available in capacities are large as 2TB. Sivaram said it's the high-end consumer devices that will see the most uptake of 64-layer 3D NAND first. As it expands downstream, it will also find its way into mobile, embedded and then the enterprise. "Enterprise takes the longest time to qualify,” Sivaram said.  For Western Digital, 64-layer 3D NAND is now cheaper than its best 2D NAND. "Not everyone has got there yet, but everyone is getting there pretty quickly,” Sivaram said.Western Digital did do some limited production of 48-layer 3D NAND for the retail segment, but it wasn't a full-fledged node for the company, he said, and 32-layer was only done internally. "It was a necessary learning step," he said.  He said 15nm 2D NAND was "extremely aggressive” lithography. "But when you go to 3D NAND, the pitches are pretty relaxed," he said. "It's not quite as aggressive as the 15nm.”  However, 3D NAND is expensive in terms of the new tools that are needed as well as the manufacturing space. Sivaram said 64-layer is the crossover where they are getting more bits to justify the increased cost. "But even with 64 layer, three bits per cell is essential,” he said. "Three bits per cell when built right is cheaper than any 2D NAND.”  Sivaram said 64-layer 3D NAND will dominate over the next 18 months, noting that Western Digital has been sampling since this time last year. He wasn't in a position to discuss what the uncertain future of its relationship with Toshiba will mean for its 3D NAND production, nor would he talk specifics of what the company's roadmap is past 64 layers.  The next step for 3D NAND will likely be string stacking, said Jim Handy, principal analyst with Objective Analysis. This involves stacking individual 3D NAND devices on top of each other, whether it's 32, 48 or 64 layers to create a stack of 96 or 128 layers. "In theory, it could take multiples of 64 layers,” he said. "The industry doesn't know far that can go.”  As the number of layers goes up, so do the aspect ratios, said Handy, making it harder to etch a hole accurately. "There are other problems, too, but the aspect ratio is a real bugaboo,” Sivaram said.  String stacking allows for a series of holes with aspect ratios of 60 instead of having to make a single hole with 120 or 240. "What everybody is wondering about is when it will be economic enough to go from 3D NAND to some alternate technology.”  It's been nearly a decade since SanDisk said ReRAM would replace NAND after three generations, added Handy. "But now you look and everybody is already shipping their third generation 3D NAND and sampling fourth generation. 3D NAND is probably going to stick around longer than anyone originally expected.”  He said the layer count has also increased faster than anyone would have expected. "It was fueled by the fact the low layer count parts were not able to meet their cost goals. The whole point of 3D NAND was that it was supposed to be cheaper than planar, and the lower layer count devices where not.” Handy said Western Digital's and Micron's aggressive ramping suggest both have found a path to profitability for their 3D NAND; it's not clear if Samsung is doing as well as Micron or Western Digital as it uses a different technology for its 3D NAND and doesn't reveal enough information to make an assessment.  Handy said the forecast for 3D NAND to truly meet its cost and yield goals has been the middle of 2018. "We've been saying that for a couple of years. 3D NAND is still not realizing its cost goals and it's still not yielding well enough that the fabs are producing as many gigabytes as they were designed to do,” he said. "It should be a lot more profitable than it is.”  In the meantime, the ultimate ownership of Toshiba's 3D NAND business won't change the landscape too much, aside from who Western Digital is sourcing from. "A year ago, it would have been a SanDisk / Toshiba development,” he said. "The names have changed but the players have remained the same.” His short take is that whatever happens, Western Digital will still crank out flash based on the SanDisk / Toshiba technology. "It's a question of who gets the collective profits.”
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Release time:2017-06-20 00:00 reading:1053 Continue reading>>

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